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thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 1 thine electronics, inc. security e thcv217 and thcv218 v- by -one ? hs hig h-speed video data transmitter and receiver general description thcv217 and thcv218 are designed to support video data transmission between the host and display. one high-speed lane can carry up to 32bit data and 3 bits of synchronizing signals at a pixel clock frequency from 20mhz to 85mhz. the chipset, which has two high-speed data lanes, can transmit video data up to 1080p/10b/60hz. the m ax imum serial data rate is 3.4gbps/lane. features ? color depth selectable: 24(83)/32(103)bit ? single-in/single-out, single-in/dual-out, and dual-in/dual-out selectable for thcv217 ? single-in/single-out, dual-in/single-out, and dual-in/dual-out selectable for thcv218 ? ac coupling for high-speed lines ? core 1.8v, cmos io 3.3v ? package: 217(tfbga105), 218(tfbga145) ? wide frequency range ? cdr requires no external frequency reference ? spread spectrum clocking tolerant up to 30khz / 0.5% (center spread) ? v- by -one ? hs standard version1.4 compliant. product link pix el clock frequency thcv217 si/so 20mhz to 85mhz di/do si/do 40mhz to 170mhz thcv218 si/so 20mhz to 85mhz di/do di/ s o 40mhz to 170mhz si/so: single-in/single- out , di /do: dual-in/dual- out di/so: dual-in/single-out , si/do: single-in/dual- out block diagram deserializer deserializer cdr deskew & formatter pll controls thcv 218 r1[9:0] g1[9:0] b1[9:0] cont1[2:1] mode1,0 col pll bet r/f dken, dk pdn, oe betout cmos output r1[9:0] g1[9:0] b1[9:0] cont1[2:1] mode demux col bet pre r/f pdn formatter serializer serializer pll controls htpdn lockn tx 0p tx 0n thcv 217 cmos input rx 0p rx 0n dglock cmos cmos cml open drain tx 1p tx 1n hsync vsync de clkin r2[9:0] g2[9:0] b2[9:0] cont2[2:1] rx 1p rx 1n htpdn lockn hsync vsync de r2[9:0] g2[9:0] b2[9:0] cont2[2:1] clkout
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 2 thine electronics, inc. security e contents page general description ................................................................................................................................................. 1 features ................................................................................................................................................................... 1 block diagram ........................................................................................................................................................ 1 pin configuration .................................................................................................................................................... 3 pin d escription ........................................................................................................................................................ 5 functional description ............................................................................................................................................ 9 absolute maximum ratings .................................................................................................................................. 17 operating conditions ............................................................................................................................................ 17 electrical specifications ........................................................................................................................................ 18 ac timing diagrams and test circuits................................................................................................ ................. 22 thcv217 input data mapping ............................................................................................................................. 27 thcv217 input data mapping (continued) ......................................................................................................... 28 thcv218 output data mapping .......................................................................................................................... 29 thcv218 output data mapping (continued) ...................................................................................................... 30 note ................................................................ ....................................................................................................... 31 package.................................................................................................................................................................. 32 notices and requests ................................................................................................................................ ............. 34
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 3 thine electronics, inc. security e pin configuration thcv217 1 2 3 4 5 6 7 8 9 10 11 a b10 b11 g18 g16 g14 g12 g10 r18 r16 r14 r12 a b b12 b13 g19 g17 g15 g13 g11 r19 r17 r15 r13 b c b14 b15 dvdh gnd gnd vdl vdl htpdn lockn r11 r10 c d b16 b17 dvdh cavdl cont11 cont12 d e b18 b19 dvdh gnd gnd gnd cavdl tx0n tx0p e f r20 r21 r/f gnd gnd gnd cavdl tx1n tx1p f g r22 r23 pre gnd gnd gnd cpvdl cont21 cont22 g h r24 r25 col pdn b29 b28 h j r26 r27 gnd dvdh demux reserved 0 mode dvdh bet clkin de j k r28 r29 g23 g25 g27 g29 b21 b23 b25 b27 vsync k l g20 g21 g22 g24 g26 g28 b20 b22 b24 b26 hsync l 1 2 3 4 5 6 7 8 9 10 11 top view
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 4 thine electronics, inc. security e thcv218 1 2 3 4 5 6 7 8 9 10 11 12 13 a hsync b19 b17 b15 b13 b11 g19 g17 g15 g13 g11 g10 r19 a b de vsync b18 b16 b14 b12 b10 g18 g16 g14 g12 r18 r17 b c cont11 cont12 reserved 4 reserved 1 vdl vdl dvdh dvdh dvdh dvdh dvdh r16 r15 c d htpdn lockn reserved 3 dvdh r14 r13 d e betout reserved 5 cavdl gnd gnd gnd gnd gnd dvdh r12 r11 e f rx0n rx0p cavdl gnd gnd gnd gnd gnd dvdh dvdh r10 f g reserved 6 reserved 7 cavdl gnd gnd gnd gnd gnd gnd gnd clkout g h rx1n rx1p cavdl gnd gnd gnd gnd gnd dvdh cont22 cont21 h j mode1 bet cavdl gnd gnd gnd gnd gnd dvdh b29 b28 j k pll mode0 dk dvdh b27 b26 k l pdn oe col dken vdl vdl dvdh dvdh dvdh dvdh dvdh b25 b24 l m r/f r21 r23 r25 r27 r29 g21 g23 g25 g27 g29 b23 b22 m n dglock r20 r22 r24 r26 r28 g20 g22 g24 g26 g28 b21 b20 n 1 2 3 4 5 6 7 8 9 10 11 12 13 top view
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 5 thine electronics, inc. security e pin description thcv217 thcv217 pin description name ball # type* description tx0n,tx0p e10,e11 co cml output for lane0 tx1n,tx1p f10,f11 co cml output for lane1. must be left open when not used. r19-r10 b8,a8,b9,a9, b10,a10,b11, a11,c10,c11 i3 1st pixel data inputs g19-g10 b3,a3,b4,a4, b5,a5,b6, a6,b7,a7 i3 1st pixel data inputs b19-b10 e2,e1,d2,d1, c2,c1,b2, b1,a2,a1 i3 1st pixel data inputs cont11,12 d10,d11 i3 user defined data inputs, serialized with 1st pixel data. active only in 10bit mode. r29-r20 k2,k1,j2,j1, h2,h1,g2, g1,f2,f1 i3 2nd pixel data inputs g29-g20 k6,l6,k5,l5, k4,l4,k3, l3,l2,l1 i3 2nd pixel data inputs b29-b20 h10,h11,k10, l10,k9,l9, k8,l8,k7,l7 i3 2nd pixel data inputs cont21,22 g10,g11 i3 user defined data inputs, serialized with 2nd pixel data. active only in 10bit mode. de j11 i3 de input hsync l11 i3 hsync input vsync k11 i3 vsync input clkin j10 i3 pixel clock input htpdn c8 i3l hot plug detect input. must be connected to rx htpdn with a 10kw pull-up resistor. lockn c9 i3l lock detect input. must be connected to rx lockn with a 10kw pull-up resistor. *type symbol co=cml output i3=3.3v cmos input, i3l=low speed 3.3v cmos input o3=3.3v cmos output p=1.8v power supply, p3=3.3v power supply
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 6 thine electronics, inc. security e thcv217 pin description (continued) name ball # type* description pdn h9 i3 power down input h: normal operation l: power down col h3 i3 color depth select input h: 8bit mode l: 10bit mode pre g3 i3 pre emphasis level select input h: 100% l: 0% bet j9 i3l field bet enable h: enable l: normal operation demux j5 i3 mode j7 i3l r/f f3 i3 input clock triggering edge select input for latching input data h: rising edge l: falling edge reserved0 j6 i3 reserved inputs. must be tied to gnd vdl c6,c7 p 1.8v power supply pins for digital circuitry cavdl d9,e9,f9 p 1.8v power supply pins for cml outputs cpvdl g9 p 1.8v power supply pins for pll circuitry dvdh c3,d3,e3,j4,j8 p3 3.3v power supply pins for ttl inputs gnd c4,c5,e5,e6,e7,f5, f6,f7,g5,g6,g7,j3 gnd ground pins *type symbol co=cml output i3=3.3v cmos input, i3l=low speed 3.3v cmos input o3=3.3v cmos output p=1.8v power supply, p3=3.3v power supply operation mode select input demux,mode=hh: reserved (forbidden) hl: single-in/dual-out lh: single-in/single-out ll: dual-in/dual-out
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 7 thine electronics, inc. security e thcv218 thcv218 pin description pin name ball # type* description rx0n,rx0p f1,f2 ci cml input for lane0 rx1n,rx1p h1,h2 ci cml input for lane1. must be left open when not used. r19-r10 a13,b12,b13, c12,c13,d12, d13,e12,e13,f13 o3 1st pixel data outputs g19-g10 a7,b8,a8,b9, a9,b10,a10, b11,a11,a12 o3 1st pixel data outputs b19-b10 a2,b3,a3,b4, a4,b5,a5, b6,a6,b7 o3 1st pixel data outputs cont11,12 c1,c2 o3 user defined data outputs. active only in 10bit mode. r29-r20 m6,n6,m5,n5, m4,n4,m3, n3,m2,n2 o3 2nd pixel data outputs g29-g20 m11,n11,m10, n10,m9,n9, m8,n8,m7,n7 o3 2nd pixel data outputs b29-b20 j12,j13,k12, k13,l12,l13, m12,m13,n12,n13 o3 2nd pixel data outputs cont21,22 h13,h12 o3 user defined data outputs. active only in 10bit mode. de b1 o3 de output vsync b2 o3 vsync output hsync a1 o3 hsync output clkout g13 o3 pixel clock output htpdn d1 od3 hot plug detect output. must be connected to tx htpdn with a 10kw pull-up resistor. hi-z : when pdn=l, l: when pdn=h lockn d2 od3 lock detect output. must be connected to tx lockn with a 10kw pull-up resistor. it drives low when the cdr locks to the incoming data. pdn l1 i3 power down input h: normal operation l: power down col l3 i3 color depth select input h: 8bit mode l: 10bit mode bet j2 i3l field bet enable h: enable l: normal operation when bet=high, reserved7 must be low. mode1,0 j1,k2 i3 operation mode select input hh: reserved (forbidden) hl: single-in/single-out lh: dual-in/single-out ll: dual-in/dual-out *type symbol ci=cml input, od3=3.3v open drain output, o3=3.3v cmos output i3=3.3v cmos input, i3l=low speed 3.3v cmos input, i3pu=3.3v cmos inout with an on-chip pullup resistor p=1.8v power supply, p3=3.3v power supply
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 8 thine electronics, inc. security e table 1. output control thcv218 pin description (continued) pin name ball # type* description pll k1 i3 pll bandwidth select h: clkin<40mhz, when siso,dido l: normal operation oe l2 i3 output enable input (see table 1 for details) h: all cmos outputs enabled l: all cmos outputs disabled, except for lockn, htpdn dglock n1 i3pu connect all dglock pins in multiple-chip configuration. must be left open for single-chip configuration. r/f m1 i3 output clock triggering edge select input h: rising edge l: falling edge dken l4 i3 dk enable h: dk enabled l: dk disabled (default) dk k3 i3 output clock delay timing select input. enabled by dken. h: late l: early refer to figure 10 for details. betout e1 o3 field bet result output. must be left open when not used. reserved7 g2 i3 ctl bit transmission on de=low blanking period enable h: ctl bit enabled (ctl are transmitted except the 1st and the last pixel of de=low) l: ctl bit disabled (ctl are low fixed during de=low) when bet=high, reserved7 must be low. reserved3 d3 o3 reserved outputs. must be left open. reserved1, 4-6 c4,c3,e2,g1 i3 reserved input. must be tied to gnd vdl c5,c6,l5,l6 p 1.8v power supply pins for digital circuitry cavdl e3,f3,g3,h3,j3 p 1.8v power supply pins for cml inputs and pll circuitry dvdh c7,c8,c9,c10,c11, d11,e11,f11,f12, h11,j11,k11,l7, l8,l9,l10,l11 p3 3.3v power supply pins for ttl outputs gnd e5,e6,e7,e8,e9,f5, f6,f7,f8,f9,g5,g6, g7,g8,g9,g11, g12,h5,h6,h7,h8, h9,j5,j6,j7,j8,j9 gnd ground pins *type symbol ci=cml input, od3=3.3v open drain output, o3=3.3v cmos output i3=3.3v cmos input, i3l=low speed 3.3v cmos input, i3pu=3.3v cmos inout with an on-chip pullup resistor p=1.8v power supply, p3=3.3v power supply pdn oe r/g/b/cont h,vsync,de,clkout l l hi-z l h all low h l hi-z h h data out
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 9 thine electronics, inc. security e functional description functional overview with v- by -one ? hs s proprietary encoding scheme and cdr (clock and data recovery) architecture, thcv217 and thcv218 enable transmission of 8/10 bit rgb, 2bits of user-defined data (cont), synchronizing signals hsync, vsync, and de by single/dual differential pair cable with minimal external components. thcv217, the transmitter, inputs cmos data (including video data, cont, hsync, vsync, and de) and serializes video data and synchronizing signals separately, depending on the polarity of de. de is a signal which indicates whether video or synchronizing data are active. when de is high, it serializes video data inputs into differential data streams. and it transmits serialized synchronizing data when de is low. figure 1 is the conceptual diagram of the basic operation of the chipset. thcv218, the receiver, automatically extracts the clock from the incoming data streams and converts the serial data into video data with de being high or synchronizing data with de being low, recognizing which type of serial data is being sent by the transmitter. and it outputs the recovered data in the form of cmos data. thcv218 can operate for a wide range of a serial bit rate from 600mbps to 3.4gbps/channel. figure 2 shows the timing diagram of the basic operation of the chipset. it does not need any external frequency reference, such as a crystal oscillator. data enable there are some requirements for de signal as described in figure 1 , figure 2 , and table 18 . if de=low, control data of same cycle and possibly particular assigned data bit ctl except the first and the last pixel are transmitted. otherwise video data are transmitted during de=high. control data from receiver in de=high period are previous data of de transition. see figure 2 . the length of de being low and high is at least 2 clock cycles long, as described in table 18 . data enable must be toggled like high -> low -> high at regular interval. ctl bit transmission there are particular assigned data bit ctl which can be transmitted both on de=high and on de=low except the first and the last pixel on de=low. this function is enabled by setting thcv218 reserved7 pin to high. )ljxuh conceptual diagram of the basic operation of the chipset data bit : r/g/b, cont control bit : v,hsync data bit : ctl* h l de thcv218 thcv217 r/g/b, cont, ctl v,hsync de=h, r/g/b,cont de=l, ctl* except the 1st and the last pixel other r/g/b,cont=low fixed de=h, v,hsync=fixed de=l, v,hsync de *ctl are particular assigned bit among r/g/b, cont that can carry arbitrary data during de=low period. *ctl bit transmission is activated by setting thcv218 reserved7 pin to high.
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 10 thine electronics, inc. security e figure 2. data and synchronizing signals transmission timing diagram note: the period between rising edges of de(tdeint),high time of de(tdeh) s hould always satisfy following equations. tdeh = ttcip (2m) tdeint = ttcip (2n) tdel >= 4ttcip (this tdel rule is only in sido mode.) m,n = positive integer , m n r equirement for de minimum length limitation is described in table 18 . figure2-1. de input timing ttcip tdeh tdel de high active period low blanking period high active period low blanking period low blanking period h,v sync r/g/b cont invalid invalid valid data valid data valid data valid data valid data thcv217 particular assigned bits ctl are transmitted except the first and last pixel of blanking (de=low) period when thcv218 reserved7 pin is set to high. /others are low fixed. tdeh tdel de high active period low blanking period high active period low blanking period low blanking period h,v sync r/g/b cont valid data valid data valid data valid data valid data thcv218 keep the last data of de=low period keep the last data of de=low period low low low low trcp ttcip clkin de tdeint tdeh tdel
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 11 thine electronics, inc. security e operation mode and color depth mode function thcv217 and 218 support a variety of operation modes to optimize power consumption, number of pcb traces, or signal integrity. refer to table 2 , table 3 , and figure 3 for details. table 2. thcv217 operation mode select 7deoh 7+&9rshudwlrqprghvhohfw clkin range # of data tx0/1 range # of lanes l l l 10bit dual-in/dual-out 20 to 85 mhz (32+3)2 0.8 to 3.4gbps 2 l l h 10bit single-in/single-out 20 to 85 mhz (32+3)1 0.8 to 3.4gbps 1 l h l 10bit single-in/dual-out 40 to 170 mhz (32+3)1 0.8 to 3.4gbps 2 l h h reserved (forbidden) - - - - h l l 8bit dual-in/dual-out 20 to 85 mhz (24+3)2 0.6 to 2.55gbps 2 h l h 8bit single-in/single-out 20 to 85 mhz (24+3)1 0.6 to 2.55gbps 1 h h l 8bit single-in/dual-out 40 to 170 mhz (24+3)1 0.6 to 2.55gbps 2 h h h reserved (forbidden) - - - - demux col cmos input cml output description mode rx0/1 range # of lanes clkout range # of data l l l 10bit dual-in/dual-out 0.8 to 3.4gbps 2 20 to 85 mhz (32+3)2 l l h 10bit dual-in/single-out 0.8 to 3.4gbps 2 40 to 170 mhz (32+3)1 l h l 10bit single-in/single-out 0.8 to 3.4gbps 1 20 to 85 mhz (32+3)1 l h h reserved (forbidden) - - - - h l l 8bit dual-in/dual-out 0.6 to 2.55gbps 2 20 to 85 mhz (24+3)2 h l h 8bit dual-in/single-out 0.6 to 2.55gbps 2 40 to 170 mhz (24+3)1 h h l 8bit single-in/single-out 0.6 to 2.55gbps 1 20 to 85 mhz (24+3)1 h h h reserved (forbidden) - - - - col mode1 mode0 description cmos output cml input
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 12 thine electronics, inc. security e figure 3. operation modes of the chipset (10bit/8bit) cml buffer figure 4. cml buffer scheme 217 217 85mhz 170mhz 218 218 217 3.4/2.55gbps 218 thcv217 thcv218 dido siso sido/ diso sido diso 85mhz 3.4/2.55gbps 3.4/2.55gbps 170mhz 85mhz 3.4/2.55gbps 3.4/2.55gbps 3.4/2.55gbps 3.4/2.55gbps 85mhz 85mhz 3.4/2.55gbps 85mhz 3.4/2.55gbps 3.4/2.55gbps cavdl txn + rxn + txn - rxn - vterm 1.3v zdiff=100? c=75 200nf 50 n=0,1 cavdl cagnd thcv217 thcv218 cml transmitter cml receiver 50 c=75 200nf n=0,1
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 13 thine electronics, inc. security e lock detect and hot-plug function lockn and htpdn of rx must be connected with those of tx as in figure 5 . lockn and htpdn on thcv218 are both open drain outputs. pull-up resistors are needed at tx side. if thcv218 is not active (in the power down mode, powered off, or not connected), thcv218 s htpdn turns high-z, and the pull-up resister at the tx side makes the htpdn input of thcv217 high. thcv217 then enters into the power down mode. wh en thcv218 is active, htpdn is pulled down by thcv218. then thcv217 starts up and transmits the training pattern for link training. l ockn indicates whether thcv218 is in the lock state or not. if thcv218 is not the lock state, lockn turns high-z. otherwise (in the lock state), its pulled down by thcv218. thcv217 keeps transmitting the training pattern until lockn turns low. and then thcv217 starts transmitting serialized input data. figure 5. hot-plug and lock detect scheme htpdn connection between thcv217 and thcv218 can be omitted as an application option. in this case, htpdn at the transmitter side should always be taken as low. see figure 6 . figure 6. htpdn is not connected scheme power supply for htpdn (tx side) power supply for lockn (tx side) htpdn lockn thcv217 thcv218 10k 10k power supply for lockn (tx side) htpdn lockn thcv217 thcv218 htpdn 10k
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 14 thine electronics, inc. security e pre-emphasis pre-emphasis can equalize severe signal degradation caused by long-distance or high-speed transmission. the pre pin selects the strength of pre-emphasis. see table 4 . pre description h w/ 100% pre - emphasis l w/o pre - emphasis table 4. pre-emphasis function table power down function setting the pdn pin low places thcv217 in the power-down mode. all the internal circuitry turns off and the tx mp /n (m=0, 1) outputs turn to ca vdl. setting the pdn pin low places thcv218 in the power-down mode. all the internal circuitry turns off and the cmos outputs drives low.
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 15 thine electronics, inc. security e field bet operation in order to help users to debug high-speed serial links (cml lines), thcv217 and thcv218 have an operation mode in which they act as the bit error tester (bet). in this mode, thcv217 internally generates a test pattern, which is then serialized onto cml high-speed lines. thcv218 receives the data stream and checks the sampled data for bit errors. this "field bet" mode is activated by setting bet = h on thcv217, and bet=h and reserved7=l on thcv218. in the field bet mode, the on-chip pattern generator on thcv217 is enabled and generates the test pattern as long as the clock is applied onto clkin. other cmos data inputs are ignored. the generated data pattern is then 8b/10b encoded, scrambled, and serialized onto cml channels. as for thcv218, the internal test pattern check circuit gets enabled and the pattern check result is output on betout. the betout pin goes low whenever bit errors occur, and it stays high when there is no bit error. please refer to figure 7 and figure 8 . table 5 shows possible combinations of tx and rx for normal operation and field bet operation. figure 7. field bet configuration figure 8. relationship between bit error and betout tx rx 1 thcv217 thcv218 2 thcv215 thcv218 3 thcv217 thcv 21 6 table 5. possible combinations of tx and rx for field bet mode thcv217 thcv218 clkin bet=h bet=h test pattern checker test pattern generator ttl data inputs are ignored betout test point for field bet reserved7=l rxmp/n m=0,1 betout thcv217,218 bet field bet operation normal operation bit error bit error
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 16 thine electronics, inc. security e dglock in order to reduce the number of cables needed for htpdn and lockn in multiple-rx chip configuration, thcv218 is equipped with the dglock pin. when all the dglock pins are connected as in figure 9 , the connected rx chips can share the cdr lock status, making all the rx chips in the same operation status. )ljxuh usage of dglock in multiple-rx configuration pll frequency range select the thcv218s pll input pin selects the operating frequency range of thcv218. table 6 shows the selectable frequency ranges for operation modes. operation mode pll clkout dual - in/dual - out h 20 to 40mhz l 40 to 85mhz dual - in/single - out h forbidden l 40 to 170mhz single - in/single - out h 20 to 40mhz l 40 to 85mhz table 6. frequency r ange select htpdn lockn rx0p/n rx1p/n rx2p/n rx3p/n open v-by-one rx v-by-one rx htpdn lockn dglock v-by-one tx dglock htpdn lockn open
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 17 thine electronics, inc. security e absolute maximum ratings table 7. thcv217 absolute maximum ratings 7deoh 7+&9$evroxwh0d[lpxp5dwlqjv operating conditions table 9. thcv217 operating conditions 7deoh 7+&92shudwlqj&rqglwlrqv ? absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. they are not meant to imply that the device should be operated at these limits. the tables of electrical characteristics specify conditions for device operation. parameter min. typ. max. units 1.8v supply voltage vdl,cavdl,cpvdl -0.3 - +2.1 v 3.3v supply voltage (dvdh) -0.3 - +4.0 v cmos intput voltage -0.3 - dvdh+0.3 v cml transmitter output voltage -0.3 - cavdl+0.3 v cml output current -50 - 50 ma storage temperature -55 - +125 junction temperature - - +125 reflow peak temperature/time - - +260/10sec maximum power dissipation @+25 w 2.47 parameter min. typ. max. units 1.8v supply voltage (vdl,cavdl) -0.3 - +2.1 v 3.3v supply voltage (dvdh) -0.3 - +4.0 v cmos input voltage -0.3 - dvdh+0.3 v cmos output voltage -0.3 - dvdh+0.3 v cmos open drain output voltage -0.3 - +4.0 v cml receiver input voltage -0.3 - cavdl+0.3 v storage temperature -55 - +125 junction temperature - - +125 reflow peak temperature/time - - +260/10sec maximum power dissipation @+25 w 2.7 prameter min. typ. max. units 1.8v supply voltage vdl,cavdl,cpvdl 1.62 1.80 1.98 v 3.3v supply voltage(dvdh) 3.00 3.30 3.60 v operating temperature -20 - 85 parameter min. typ. max. units 1.8v supply voltage vdl,cavdl,cpvdl 1.62 1.80 1.98 v 3.3v supply voltage(dvdh) 3.00 3.30 3.60 v operating temperature -20 - 85
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 18 thine electronics, inc. security e electrical specificatio ns 3.3v cmos dc specifications table 11. thcv217and thcv218 3.3v cmos dc specifications cml dc specifications table 12. thcv217 cml dc specifications 7deoh 7+&9&0/'&6shflilfdwlrqv symbol parameter conditions min. typ. max. units i3,i3pu 2.0 - dvdh v i3l 2.0 - dvdh v i3,i3pu 0 - 0.8 v i3l 0 - 0.7 v voh high level output voltage o3 ioh=-8ma 2.4 - - v o3 iol=8ma - - 0.4 v od3,i3pu iol=4ma - - 0.4 v iih input leak current high vin=dvdh - - 10 ua iil input leak current low vin=0v - - 10 ua iozh output leak current high in high-z state vin=dvdh, oe=l - - 10 ua iozl output leak current low in high-z state vin=0v, oe=l - - 10 ua low level output voltage vih vil vol high level input voltage low level input voltage symbol parameter conditions min. typ. max. units vtod cml differential mode output voltage pre=l 200 300 400 mv pre=l - 0 - % pre=h 80 100 120 % pre=l mv pre=h mv itoh cml output leak current high pdn=h - - 10 ua itos cml output short circuit current cavdl=1.8v -90 - - ma pre cml pre-emphasis level cavdl-2vtod cavdl-vtod vtoc cml common mode output voltage symbol parameter conditions min. typ. max. units vrth cml differential input high threshold - - 50 mv vrtl cml differential input low threshold -50 - - mv irih cml input leak current high pdn=l, rx0/1=cavdl - - 10 ua iril cml input leak current low pdn=l,rx0/1=0v - - 10 ua irrih cml input current high rx0/1=cavdl - - 2 ma irril cml input current low rx0/1=0v -6 - - ma rrin cml differential input resistance 80 100 120 ?
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 19 thine electronics, inc. security e supply currents table 14. thcv217 supply currents 7deoh 7+&96xsso\&xuuhqwv symbol parameter conditions min. typ. max. units dido 10bit pre = h - - 185 ma siso 10bit pre = h - - 115 ma sido 10bit pre = h - - 180 ma dido 10bit pre = h - - 10 ma siso 10bit pre = h - - 7 ma sido 10bit pre = h - - 10 ma itccs transmitter power down supply current pdn = l input = fixed l or h - - 200 ua itccw33 transmitter supply current for dvdh (worst case pattern) transmitter supply current for vdl, cavdl, cpvdl (worst case pattern) itccw symbol parameter conditions min. typ. max. unit dido 10bit - - 180 ma siso 10bit - - 95 ma diso 10bit - - 170 ma dido 10bit cl=8pf - - 200 ma siso 10bit cl=8pf - - 100 ma diso 10bit cl=8pf - - 200 ma irccs receiver power down supply current pdn = l input = fixed l or h - - 200 ua receiver supply current for dvdh (worst case pattern) irccw irccw33 receiver supply current for vdl, cavdl (worst case pattern)
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 20 thine electronics, inc. security e switching characteristics table 16. thcv217 switching characteristics symbol parameter conditions min. typ. max. units ttrf tx0/1 rise and fall time (20%-80%) 50 - 150 ps ttosk tx0/1 output inter pair skew -2 - 2 ui siso, dido 11.76 - 50 ns sido 5.88 - 25 ns ttch clk in high time 0.35ttcip 0.5ttcip 0.65ttcip ns ttcl clk in low time 0.35ttcip 0.5ttcip 0.65ttcip ns tts cmos data setup to clk in 2.0 - - ns tth cmos data hold to clk in 0.5 - - ns siso / dido 8bit (13+7/10)ttcip siso / dido 10bit 13ttcip sido 8bit (21+4/10)ttcip sido 10bit 20ttcip ttpd power on to pdn high delay 0 - - ns ttpll0 pdn high to cml output delay - - 10 ms ttpll1 pdn low to cml output high fix delay - - 20 ns ttnp0 lockn high to training pattern output delay - - 10 ms ttnp1 lockn low to data pattern output delay - - 10 ms typ.+10+ttcip ttcip clkin period ttcd ns input clock to output data delay typ.-10 typ.-10-ttcip typ.+10
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 21 thine electronics, inc. security e table 17. thcv218 switching characteristics 7deoh '(uhtxluhphqw symbol parameter conditions min. typ. max. units col=l 294 - 1250 ps col=h 392 - 1667 ps trisk rx0/1 input inter pair skew margin - - 15 ui siso, dido 11.76 50.0 ns diso 5.88 25.0 ns trch clkout high time - t/2 - ns trcl clkout low time - t/2 - ns tdout cmos data out period - t - ns trs cmos data setup to clkout 0.45trcp-0.45 - - ns trh cmos data hold to clkout 0.45trcp-0.45 - - ns pll=h - 3t/16 - ns pll=l - 3t/32 - ns clock - 0.7 1.0 ns data - 1.4 2.0 ns clock - 0.7 1.0 ns data - 1.4 2.0 ns siso/dido 8bit pll=l (18+5/10)trcp siso/dido 10bit pll=l 18trcp siso/dido 8bit pll=h (16+4/10)trcp siso/dido 10bit pll=h (15+7/10)trcp diso 8bit (39+5/10)trcp diso 10bit 38trcp trpd power on to pdn high delay 0 - - ns trhpd0 pdn high to htpdn low delay - - 1 us trhpd1 pdn low to htpdn high delay - - 1 us trpll0 training pattern input to lockn low delay - - 10 ms trpll1 pdn low to lockn high delay - - 10 us trlck0 lockn low to ttl output delay - - 5 ms trlck1 lockn high to ttl low-fixed delay - - 0 ns ns input data to output clock delay trbit unit interval tthl cmos high to low transition time ttlh cmos low to high transition time tdk clkout delay time trdc typ.-10 typ.+10 t trcp clkout period symbol parameter conditions min. typ. max. units tdeh de=high duration 2ttcip - - sec siso, dido 2ttcip - - sec sido, diso 4ttcip - - sec tdel de=low duration
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 22 thine electronics, inc. security e ac timing diagrams and test circuits cmos input switching characteristics figure 10. cmos input switching timing diagrams r/f=l r/f=h tts tth ttcl ttch ttcip dvdh/2 dvdh/2 dvdh/2 clkin rx.gx,bx x=29-20,19-10 hsync,vsync de cont11,12 cont21,22 dvdh/2 dvdh/2
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 23 thine electronics, inc. security e cmos output switching characteristics figure 11. cmos output switching timing diagrams and test circuit 20% 80% ttlh tthl c l = 8pf r d = 39 test point r/f=l r/f=h r/f=l r/f=h clkout dken=l clkout dken=h dk=l clkout dken=h dk=h rx.gx,bx x=29-20,19-10 hsync,vsync de cont11,12 cont21,22 dvdh/2 dvdh/2 dvdh/2 dvdh/2 dvdh/2 dvdh/2 dvdh/2 r/f=h r/f=l trcp trs trh tdout trcl trch tdk tdk
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 24 thine electronics, inc. security e cml output switching characteristics figure 12. cml output switching timing diagrams and test circuit cml input switching characteristics figure 13. cml input timing diagrams txmp txmn m=0,1 75 200nf 75 200nf < 5mm 20% 80% vdiff = (txmp) - (txmn) ttrf ttrf 50? 50? m=0,1 vdiff = (tx0p) - (tx0n) vdiff = (tx1p) - (tx1n) ttosk vdiff = 0v vdiff = 0v vdiff = (rx0p) - (rx0n) vdiff = (rx1p) - (rx1n) trisk vdiff = 0v vdiff = 0v
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 25 thine electronics, inc. security e latency characteristics figure 14. thcv217 and thcv218 latency ttcd vdiff = (tx0p) - (tx0n) pixel 1st bit r/f=l r/f=h dvdh/2 dvdh/2 dvdh/2 clkin rx.gx,bx x=29-20,19-10 hsync,vsync de cont11,12 cont21,22 ttcip vdiff = (rx0p) - (rx0n) trdc pixel 1st bit r/f=l r/f=h clkout dken=l rx.gx,bx x=29-20,19-10 hsync,vsync de cont11,12 cont21,22 dvdh/2 dvdh/2 dvdh/2 ttcip
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 26 thine electronics, inc. security e lock and unlock sequence figure 15. thcv217 and thcv218 lock and unlock sequence ttpd and trpd minimum is 0sec; therefore, pdn can be applied at the same time as vdl, cavdl, cpvdl and dvdh. ttpll0 is the time from both pdn=high and htpdn=low moment to training pattern ignition. htpdn could transit from high to low under pdn=high condition at thcv217, which is different from what figure 15 indicates but is natural situation. note: when change and discontinuation occur in the clock frequency to thcv217, in order to collateralize the operation after clock frequency change or return, please insert a low pulse to the pdn pin of thcv218 to reset the internal pll. power on vdl cavdl cpvdl dvdh htpdn pdn lockn fix to cavdl cdr training pattern aln training pattern cdr training pattern ttpll0 ttnp1 ttnp0 ttpll1 txn 1.5v ttpd normal pattern low-level normal pattern clkin data pattern rx/gx/bx conty x=29-20,19-10 y=22,21,12,11 n=1,0 rxn power on vdl cavdl dvdh htpdn pdn lockn cdr training pattern trhpd0 trpll0 trhpd1 trlck0 trlck1 1.5v trpd aln training pattern normal pattern trpll1 low low valid data pattern clkout rx/gx/bx conty low low
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 27 thine electronics, inc. security e thcv217 input data mapping table 19. cmos input data mapping for single-in/single- out , single-in/dual-out mode 10bit (30bpp) 8bit (24bpp) 10bit (30bpp) 8bit (24bpp) r0*1 - r10 - d30 r1*1 - r11 - d31 r2 r0 r12 r12 d0 r3 r1 r13 r13 d1 r4 r2 r14 r14 d2 r5 r3 r15 r15 d3 r6 r4 r16 r16 d4 r7 r5 r17 r17 d5 r8 r6 r18 r18 d6 r9 r7 r19 r19 d7 g0*1 - g10 - d28 g1*1 - g11 - d29 g2 g0 g12 g12 d8 g3 g1 g13 g13 d9 g4 g2 g14 g14 d10 g5 g3 g15 g15 d11 g6 g4 g16 g16 d12 g7 g5 g17 g17 d13 g8 g6 g18 g18 d14 g9 g7 g19 g19 d15 b0*1 - b10 - d26 b1*1 - b11 - d27 b2*1 b0*1 b12 b12 d16 b3*1 b1*1 b13 b13 d17 b4*1 b2*1 b14 b14 d18 b5*1 b3*1 b15 b15 d19 b6*1 b4*1 b16 b16 d20 b7*1 b5*1 b17 b17 d21 b8*1 b6*1 b18 b18 d22 b9*1 b7*1 b19 b19 d23 cont1*1*2 - cont11 - d24 cont2*1*2 - cont12 - d25 hsync hsync hsync hsync hsync vsync vsync vsync vsync vsync de de de de de *1 ctl bits, which are carried during de=low except the 1st and the last pixel. *2 3d flags defined in the v-by-one? hs standard are assigned to the following bit. v-by-one? hs standard packer/unpacker d[24](3dlr) <=> cont2 v-by-one? hs standard packer/unpacker d[25](3den) <=> cont1 data signals transm itter input pin nam e sym bol defined by v-by-one? hs
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 28 thine electronics, inc. security e thcv217 input data mapping (continued) table 20. cmos input data mapping for dual-in/dual-out mode 10bit (30bpp) 8bit (24bpp) 10bit (30bpp) 8bit (24bpp) 10bit (30bpp) 8bit (24bpp) 10bit (30bpp) 8bit (24bpp) r10*1 - r10 - r20*1 - r20 - d30 r11*1 - r11 - r21*1 - r21 - d31 r12 r10 r12 r12 r22 r20 r22 r22 d0 r13 r11 r13 r13 r23 r21 r23 r23 d1 r14 r12 r14 r14 r24 r22 r24 r24 d2 r15 r13 r15 r15 r25 r23 r25 r25 d3 r16 r14 r16 r16 r26 r24 r26 r26 d4 r17 r15 r17 r17 r27 r25 r27 r27 d5 r18 r16 r18 r18 r28 r26 r28 r28 d6 r19 r17 r19 r19 r29 r27 r29 r29 d7 g10*1 - g10 - g20*1 - g20 - d28 g11*1 - g11 - g21*1 - g21 - d29 g12 g10 g12 g12 g22 g20 g22 g22 d8 g13 g11 g13 g13 g23 g21 g23 g23 d9 g14 g12 g14 g14 g24 g22 g24 g24 d10 g15 g13 g15 g15 g25 g23 g25 g25 d11 g16 g14 g16 g16 g26 g24 g26 g26 d12 g17 g15 g17 g17 g27 g25 g27 g27 d13 g18 g16 g18 g18 g28 g26 g28 g28 d14 g19 g17 g19 g19 g29 g27 g29 g29 d15 b10*1 - b10 - b20*1 - b20 - d26 b11*1 - b11 - b21*1 - b21 - d27 b12*1 b10*1 b12 b12 b22*1 b20*1 b22 b22 d16 b13*1 b11*1 b13 b13 b23*1 b21*1 b23 b23 d17 b14*1 b12*1 b14 b14 b24*1 b22*1 b24 b24 d18 b15*1 b13*1 b15 b15 b25*1 b23*1 b25 b25 d19 b16*1 b14*1 b16 b16 b26*1 b24*1 b26 b26 d20 b17*1 b15*1 b17 b17 b27*1 b25*1 b27 b27 d21 b18*1 b16*1 b18 b18 b28*1 b26*1 b28 b28 d22 b19*1 b17*1 b19 b19 b29*1 b27*1 b29 b29 d23 cont11*1*2 - cont11 - cont21*1*2 - cont21 - d24 cont12*1*2 - cont12 - cont22*1*2 - cont22 - d25 hsync hsync hsync hsync - - - - hsync vsync vsync vsync vsync - - - - vsync de de de de - - - - de *1 ctl bits, which are carried during de=low except the 1st and the last pixel. *2 3d flags defined in the v-by-one? hs standard are assigned to the following bit. v-by-one? hs standard packer/unpacker d[24](3dlr) <=> cont12/cont22 v-by-one? hs standard packer/unpacker d[25](3den) <=> cont11/cont21 sym bol defined by v-by-one? hs 1st pixel data 2nd pixel data data signals transm itter input pin nam e data signals transm itter input pin nam e
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 29 thine electronics, inc. security e thcv218 output data mapping table 21. cmos output data mapping for single-in/single- out , dual-in/single- out mode 10bit (30bpp) 8bit (24bpp) 10bit (30bpp) 8bit (24bpp) r0*1 - r10 - d30 r1*1 - r11 - d31 r2 r0 r12 r12 d0 r3 r1 r13 r13 d1 r4 r2 r14 r14 d2 r5 r3 r15 r15 d3 r6 r4 r16 r16 d4 r7 r5 r17 r17 d5 r8 r6 r18 r18 d6 r9 r7 r19 r19 d7 g0*1 - g10 - d28 g1*1 - g11 - d29 g2 g0 g12 g12 d8 g3 g1 g13 g13 d9 g4 g2 g14 g14 d10 g5 g3 g15 g15 d11 g6 g4 g16 g16 d12 g7 g5 g17 g17 d13 g8 g6 g18 g18 d14 g9 g7 g19 g19 d15 b0*1 - b10 - d26 b1*1 - b11 - d27 b2*1 b0*1 b12 b12 d16 b3*1 b1*1 b13 b13 d17 b4*1 b2*1 b14 b14 d18 b5*1 b3*1 b15 b15 d19 b6*1 b4*1 b16 b16 d20 b7*1 b5*1 b17 b17 d21 b8*1 b6*1 b18 b18 d22 b9*1 b7*1 b19 b19 d23 cont1*1*2 - cont11 - d24 cont2*1*2 - cont12 - d25 hsync hsync hsync hsync hsync vsync vsync vsync vsync vsync de de de de de *1 ctl bits, which are carried during de=low except the 1st and the last pixel. *2 3d flags defined in the v-by-one? hs standard are assigned to the following bit. v-by-one? hs standard packer/unpacker d[24](3dlr) <=> cont2 v-by-one? hs standard packer/unpacker d[25](3den) <=> cont1 data signals transm itter input pin nam e sym bol defined by v-by-one? hs
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 30 thine electronics, inc. security e thcv218 output data mapping (continued) table 22. cmos output data mapping for dual-in/dual- out mode 10bit (30bpp) 8bit (24bpp) 10bit (30bpp) 8bit (24bpp) 10bit (30bpp) 8bit (24bpp) 10bit (30bpp) 8bit (24bpp) r10*1 - r10 - r20*1 - r20 - d30 r11*1 - r11 - r21*1 - r21 - d31 r12 r10 r12 r12 r22 r20 r22 r22 d0 r13 r11 r13 r13 r23 r21 r23 r23 d1 r14 r12 r14 r14 r24 r22 r24 r24 d2 r15 r13 r15 r15 r25 r23 r25 r25 d3 r16 r14 r16 r16 r26 r24 r26 r26 d4 r17 r15 r17 r17 r27 r25 r27 r27 d5 r18 r16 r18 r18 r28 r26 r28 r28 d6 r19 r17 r19 r19 r29 r27 r29 r29 d7 g10*1 - g10 - g20*1 - g20 - d28 g11*1 - g11 - g21*1 - g21 - d29 g12 g10 g12 g12 g22 g20 g22 g22 d8 g13 g11 g13 g13 g23 g21 g23 g23 d9 g14 g12 g14 g14 g24 g22 g24 g24 d10 g15 g13 g15 g15 g25 g23 g25 g25 d11 g16 g14 g16 g16 g26 g24 g26 g26 d12 g17 g15 g17 g17 g27 g25 g27 g27 d13 g18 g16 g18 g18 g28 g26 g28 g28 d14 g19 g17 g19 g19 g29 g27 g29 g29 d15 b10*1 - b10 - b20*1 - b20 - d26 b11*1 - b11 - b21*1 - b21 - d27 b12*1 b10*1 b12 b12 b22*1 b20*1 b22 b22 d16 b13*1 b11*1 b13 b13 b23*1 b21*1 b23 b23 d17 b14*1 b12*1 b14 b14 b24*1 b22*1 b24 b24 d18 b15*1 b13*1 b15 b15 b25*1 b23*1 b25 b25 d19 b16*1 b14*1 b16 b16 b26*1 b24*1 b26 b26 d20 b17*1 b15*1 b17 b17 b27*1 b25*1 b27 b27 d21 b18*1 b16*1 b18 b18 b28*1 b26*1 b28 b28 d22 b19*1 b17*1 b19 b19 b29*1 b27*1 b29 b29 d23 cont11*1*2 - cont11 - cont21*1*2 - cont21 - d24 cont12*1*2 - cont12 - cont22*1*2 - cont22 - d25 hsync hsync hsync hsync - - - - hsync vsync vsync vsync vsync - - - - vsync de de de de - - - - de *1 ctl bits, which are carried during de=low except the 1st and the last pixel. *2 3d flags defined in the v-by-one? hs standard are assigned to the following bit. v-by-one? hs standard packer/unpacker d[24](3dlr) <=> cont12/cont22 v-by-one? hs standard packer/unpacker d[25](3den) <=> cont11/cont21 sym bol defined by v-by-one? hs 1st pixel data 2nd pixel data data signals receiver output pin nam e data signals receiver output pin nam e
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 31 thine electronics, inc. security e note 1 )power on sequence dont input clock nor data before th cv217 is on in order to keep absolute maximum ratings. 2 )cable connection and disconnection dont connect and disconnect the cml cable, when the power is supplied to the system. 3 )gnd connection connect the each gnd of the pcb which transmitter, receiver and th cv217-218 on it. it is better for emi reduction to place gnd cable as close to cml cable as possible. 4 )multiple device connection htpdn and lockn signals are supposed to be connected proper for their purpose like the following figure. htpdn should be from just one rx to multiple tx because its purpose is only ignition of all tx. lockn should be connected so as to indicate that all rx cdr become ready to receive normal operation data. lockn of tx side can be simply split to multiple tx. thcv218 dglock connection is appropriate for multiple rx use. also possible time difference of internal processing time (p.19 thcv217 ttcd and p.20 thcv218 trdc ) on multiple data stream must be accommodated and compensated by the following destination device connected to multiple thcv218, which may have internal fifo. thcv217 htpdn lockn thcv217 htpdn lockn thcv218 htpdn lockn dglock thcv218 htpdn lockn dglock source device destination device ex. synchronized time diff. comes up clkin.1 clkin.2 clkout.1 clkout.2 internal processing time ttcd internal processing time trdc fifo fifo
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 32 thine electronics, inc. security e package thcv21 7 tfbga 10 x 10 1 0 5l a b c d e f g h j k l 1 2 3 4 5 6 7 8 9 10 11 pin a1 corner a1 corner a b c d e f g h j k l 1234567891011 0.8 8.0 10.0 0.8 8.0 10.0 bottom view top view seating plane -c- 0.12 c 0.53 ref. 0.26 ref. 1.20 max. 0.27 0.37 unit : mm ball diameter: 0.4 ball width: 0.38 0.48
thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc. 33 thine electronics, inc. security e thcv218 tfbga 12x12 145l a b c d e f g h j k l 1 2 3 4 5 6 7 8 9 10 11 pin a1 corner a1 corner 9.6 12.0 0.8 9.6 12.0 bottom view top view seating plane -c- 0.12 c 0.53 ref. 0.26 ref. 1.20 max. 0.27 0.37 unit : mm m n 12 13 a b c d e f g h j k l 1234567891011 m n 1213 0.8 ball diameter: 0.4 ball width: 0.38 0.48
34 thine electronics, inc. security e notices and requests 1. the product specifications described in this material are subject to change without prior notice. 2. the circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. we are not responsible for possible errors and omissions in this material. please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. this material contains our copyright, know-how or other proprietary. copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. product application 5.1 application of this product is intended for and limited to the following applications: audio-video device, office automation device, communication device, consumer electronics, smartphone, feature phone, and amusement machine device. this product must not be used for applications that require extremely high-reliability/safety such as aerospace device, traffic device, transportation device, nuclear power control device, combustion chamber device, medical device related to critical care, or any kind of safety device. 5.2 this product is not intended to be used as an automotive part, unless the product is specified as a product conforming to the demands and specifications of iso/ts16949 ("the specified product") in this data sheet. thine electronics, inc. (thine) accepts no liability whatsoever for any product other than the specified product for it not conforming to the aforementioned demands and specifications. 5.3 thine accepts liability for demands and specifications of the specified product only to the extent that the user and thine have been previously and explicitly agreed to each other. 6. d espite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. please note that this product is not designed to be radiation-proof. 8. testing and other quality control techniques are used to this product to the extent thine deems necessary to support warranty for performance of this product . except where mandated by applicable law or deemed necessary by thine based on the users request, testing of all functions and performance of the product is not necessarily performed. 9. customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the foreign exchange and foreign trade control law. 10. the produ ct or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or mal function, if pins of the product are shorted by such as foreign substance. the damages may cause a smoking and ignition. therefore, you are encouraged to implement safety measures by adding protection devices , such as fuses. thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc.
34 thine electronics, inc. security e thcv217-thcv218_rev.2.11_e copyright(c)2016 thine electronics,inc.

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